The present invention relates to a switching power amplifier and a switching control method for a switching power amplifier, and particularly to a switching power amplifier and a switching power control method for the switching power amplifier suitable for being applied to the purpose of minimizing the effects of the noise generated by the switching power supply on the power amplifier stage in the switching power amplifier having a switching supply unit as a power source.
Signal amplifiers that are usually referred to as xe2x80x9cclass D-operation amplifiersxe2x80x9d are conventionally known as one type of power amplifier. A typical example of a class D-operation amplifier is shown in FIG. 7A. In the illustrated power amplifier, an analog signal S1 inputted into a signal input terminal 1 is subjected to pulse width modulation by a pulse width modulation amplifier 2. This pulse width modulation amplifier 2 generates a PWM (pulse width modulation) signal S2, in which the changes in the signal level of the analog signal S1 are expressed as changes in the pulse width direction, and also a PWM signal S3 with a waveform that is in a phase inversion relationship with the PWM signal S2.
It should be noted that in the following explanation, the waveform of the PWM signal S3 is in a phase inversion relationship with the waveform of the PWM signal S2, so that these signals have a complementary relationship whereby when one of the signal waveforms of the PWM signal S2 and S3 is positive, the signal waveform of the other signal is negative.
It is also conventionally known that the power efficiency of class D-operation amplifiers is high, but to further increase the power efficiency of a power amplifier as a whole, it is conceivable to use a switching power supply circuit as the power supply. In FIG. 7A, numeral 10 is a clock with a fixed cycle period t, so that the PWM signal S2 and the PWM signal S3 that are based on the changes in the signal level of the analog signal S1 are respectively generated and outputted by the pulse width modulation amplifier 2 as signals that are repeatedly produced in periods of t. It should be noted that the signal phase relationship between the PWM signal S2 and the PWM signal S3 is as described above, so that the signals have complementary characteristics whereby the signal phase of the PWM signal S2 is in an inverse relationship with the signal phase of the PWM signal S3.
A DC voltage that has been stabilized at a preset fixed output voltage is generated by the switching power supply unit 11 and a positive DC voltage is supplied from the positive DC power supply terminal +Vcc of the switching power supply unit 11 to the power switching circuit 3. It should be noted that the negative DC power supply terminal of the switching power supply unit 11 is grounded via an earth terminal 12. A class D-operation amplifier differs from the example amplifier shown in FIG. 7A, in that it is composed as an amplifier with a positive/negative power supply, xe2x88x92Vcc is also outputted, and a neutral point between +Vcc and xe2x88x92Vcc is grounded.
In the power switching circuit 3, the source of a first N-channel power MOSFET 4 (referred to hereafter as the xe2x80x9cfirst power FET 4xe2x80x9d) is connected to the drain of a second N-channel power MOSFET 5 (referred to hereafter as the xe2x80x9csecond power FET 5xe2x80x9d), with the drain of the first power FET 4 being connected to the positive DC power supply terminal +Vcc of the switching power supply unit 11 and the source of the second power FET 5 being connected to ground.
A circuit that is constructed in this way of the first power FET 4 and the second power FET 5 is normally referred to as a xe2x80x9chalf bridge circuitxe2x80x9d. Also, as shown in FIG. 7A, a pre-driver 28 is used as a half bridge driver that drives a half bridge circuit with the above construction. As one example, the pre-driver HIB2001B (registered trademark) that is manufactured by Intersil Corporation as a motor pre-driver can be used as this pre-driver 28.
Via this pre-driver 28, the PWM signal S2 is converted into a signal S7 that can perform an ON/OFF driving of the first power FET 4, and the PWM signal S3 is converted into a signal S8 that can perform an ON/OFF driving of the second power FET 5. The first power FET 4 is driven by the signal S7 and the second power is driven by the signal S8, so that the first power FET 4 and the second power FET 5 are alternately switched ON and OFF by the PWM signals S7 and S8. A PWM signal S4 that switches in accordance with changes in the pulse width direction of the PWM signals S7 and S8 is generated and is outputted from between a connecting point located between the source of the first power FET 4 and the drain of the second power FET 5 and the earth connection.
After the PWM signal S4 passes through a high frequency band-blocking power filter unit (hereafter referred to as the LPF (low pass filter) unit) 6 composed of a coil 7 and a capacitor 8, and then through a capacitor 13 for removing the DC component, an analog power signal S5 that reflects the changes in the signal level of the analog signal S1 within the band of audible frequencies is demodulated from the PWM power signal S4. The demodulated analog power signal S5 is supplied to the speaker unit 9, where the analog power signal S5 is reproduced as an audio signal.
FIG. 7B shows several one-sided PWM-modulated waveforms as representative examples of the PWM-modulated waveform of the PWM signal S4. It should be noted that the name xe2x80x9cone-sided PWM-modulated waveformxe2x80x9d is used since both end edges (shown as xe2x80x9cKxe2x80x9d in FIG. 7B) of the PWM-modulated waveforms are fixed by locking them at the cycle period t of the clock signal S6, and a movable edge (M), which is a falling edge of the PWM-modulated waveform generated between both end edges of a fixed PWM-modulated waveform, is position-modulated in accordance with the signal level of the analog signal S1. Such PWM modulated waveforms are continuously generated one after the other.
It should be noted that other examples of one-sided PWM-modulated waveforms are also known. Such PWM-modulated waveforms are continuously generated with both of the fixed end edges of the PWM-modulated waveforms that are locked at the cycle period t of the clock signal S6 being falling edges, and the rising edge of the PWM-modulated waveform that is generated between the two fixed edges of the PWM-modulated waveform being position-modulated in accordance with changes in the signal level of the analog signal S1.
It should be noted that in the following explanation, the edges in the waveform of the PWM signal S4 that are locked by the clock signal S6 at the timing determined by the cycle period t of the clock signal S6 are referred to as the xe2x80x9cfixed edgesxe2x80x9d of the PWM signal S4. As examples, in parts 1B, 2B, and 3B of FIG. 7B, the waveform edges illustrated using upward-pointing arrows correspond to these fixed edges. Also, in the waveform of the PWM signal S4, the edge whose position changes in accordance with the signal level of the analog signal S1 is referred to as the xe2x80x9cmovable edge Mxe2x80x9d. As examples, the waveform edges of the PWM signal S4 that are shown by horizontal-pointing arrows in parts 2B, and 3B of FIG. 7B, correspond to movable edges M.
In the following explanation, out of the fixed edges, the edge that precedes the movable edge M is referred to as the xe2x80x9cstarting edgexe2x80x9d. In the example shown in FIG. 7B, out of the two fixed edges K of the PWM-modulated waveform, the former fixed edge K, which is locked by the first waveform edge in the waveform of the clock signal S6 as shown by the upward-pointing arrow (see part 4B in FIG. 7B), is the starting edge.
In the present example of one-sided PWM-modulated waveforms, the signal waveform of the PWM power signal S4 at a point when the signal level of the analog signal S1 is zero becomes a PWM-signal waveform with a duty ratio of 50%, as shown in part 1B of FIG. 7B. The waveform of the PWM power signal S4 when the signal level of the analog signal S1 has changed from zero in the direction where positive values increase is as shown in part 2B of FIG. 7B, with the width of the part of the waveform of the PWM power signal S4 that is located between the fixed edge K that is the starting edge and the movable edge M increasing together with this change in the signal level. Conversely, when the signal level of the analog signal S1 has changed from zero in the direction where negative values increase, the waveform of the PWM power signal S4 is as shown in part 3B of FIG. 7B, with the width of the part of the waveform of the PWM power signal S4 that is located between the fixed edge K that is the starting edge and the movable edge M decreasing together with this change in the signal level.
In more detail, changes in the area that is expressed by the waveform of the PWM power signal S4 represent the changes in the signal level of the analog signal S1. Accordingly, if the changes in the area that is expressed by the waveform of the PWM power signal S4 are not correctly proportional to the changes in the waveform area between the fixed edge K and the movable edge M that are expressed by waveforms of the PWM signals S2 and S3, which is to say, when there is a proportion error, there is the problem of this error appearing as signal waveform distortion of the analog power signal S5.
FIG. 8A is a block diagram showing the principal parts of the construction of a conventional switching power supply unit 11. As shown in the drawing, the switching power supply unit 11 includes an AC power supply unit 14, a transformer 14A, a PWM switching unit 15, a rectification unit 16, a voltage error detecting unit 17, a reference voltage generating unit 18, a clock signal generating unit 19, and a switching unit 20.
One AC voltage output terminal that is provided on the AC power supply unit 14 for outputting the AC voltage S10 is connected to one end of the input coil of the transformer 14A, while the other end of the input coil is connected via the switching unit 20 to the other AC voltage output terminal that is provided on the AC power supply unit 14 for the AC voltage S10. The output coil of the transformer 14A is connected to the inputs of the rectification unit 16, with the DC voltage output terminals of the rectification unit 16 being respectively connected to the DC voltage output terminals 16A and 16B so that a DC voltage is outputted from these output terminals 16A and 16B. It should be noted that of the output terminals 16A and 16B, the output terminal 16A is the positive output terminal +Vcc for the DC voltage, while the output terminal 16B is the ground level output terminal.
In the above switching power supply unit 11, the DC voltage output side of the rectification unit 16 is inputted into the error detection input of the voltage error detecting unit 17, with a reference voltage 18A that has been generated by the reference voltage generating unit 18 being inputted into the reference voltage input of the voltage error detecting unit 17. The voltage error detecting unit 17 compares the voltage of the DC voltage output with the reference voltage 18A and generates an error voltage 18B, with this error voltage 18B being supplied to the error voltage input of the PWM control unit 15.
The power PWM control unit 15 generates a PWM signal with fixed edges that are locked by every period of the power supply clock signal S9, the PWM signal having been generated by the clock signal generating unit 19 and inputted to the clock signal input terminal of the power PWM control unit 15. When generating this PWM signal S19, the power PWM control unit 15 controls, based on the error voltage 18B, the position of the movable edge in a direction in which the error voltage 18B is to be suppressed.
The PWM signal S19 is supplied to the switching unit 20 and the ratio between the ON period and the OFF period of the switching by the switching unit 20 is controlled based on the position of the movable edge of the PWM signal S19. Accordingly, the DC voltage outputted from the output terminals 16A and 16B is supplied as described earlier to the switching circuit 3 with the voltage of the DC voltage outputted from the output terminals 16A and 16B being maintained at a preset voltage level.
On the other hand, in the switching power amplifier with a class D-operation amplifier construction as shown in FIG. 7A, when a switching operation by the switching power supply unit 11 results in a switching noise signal shown as xe2x80x9cSNxe2x80x9d in part 1D of FIG. 8B being generated while the state of the PWM power signal S4 is xe2x80x9cONxe2x80x9d as shown in FIG. 8B, the switching noise signal SN is transmitted to the power switching circuit 3 of the class D-operation amplifier, so that there is the possibility of this switching noise signal SN being superimposed on the PWM power signal S4 as shown by part 2D in FIG. 8B.
When the switching noise signal SN is superimposed on the PWM power signal S4, there is a change in the area between the fixed edge that is the starting edge and the movable edge in the pulse signal during which the level of the PWM power signal S4 is high, which as described earlier results in a proportion error being produced. This causes the problem that waveform distortion occurs in the analog power signal S5 in the audible frequency band that is demodulated from this PWM power signal S4.
It should be noted that as shown in FIG. 7, the source of the second power FET 5 is connected to ground, so that when the second power FET 5 is turned on by the signal S8, the PWM power signal S4 is fixed at the ground level. In cases where the switching power supply unit 11 is embedded on a printed circuit board, the entire surface on the opposite side of the printed circuit board on which the switching power supply unit 11 is embedded is composed of a conductor layer at the ground level (that is to say, a wide ground plane), so that the reactance between the source of the second power and the ground level becomes as close as possible to zero. Accordingly, when the PWM power signal S4 is at a low level, the generation of switching noise can be sufficiently suppressed, as shown by the symbol G in part 2D of FIG. 8B.
On the switching power supply unit 11 side also, the reactance value to the ground becomes as a close as possible to zero, so that it is possible to suppress noise that leaks from the ground side. However, there remains the problem that in order to suppress the distortion component in the PWM power signal S4, it has been difficult to sufficiently suppress the switching noise that is generated by the switching unit 20 when the switching unit 20 of the switching power supply unit 11 switches from OFF to ON so as to prevent the switching noise from being superimposed on the output of the rectification unit 16.
The present invention was conceived in view of the problem with the related art described above, and has an object of solving the problem by controlling a switching power supply unit that supplies power to a power switching unit, whose switching is controlled by a PWM signal that is generated based on changes in a signal level of an input signal S1, so that a clock signal used as a reference for the timing of switching operations from an OFF state to an ON state is generated during a period during which there is no effect on a PWM power signal that is outputted by the power switching unit and supplied to the load.
A switching power amplifier according to the present invention is equipped with a switching power supply unit and includes: a PWM (pulse width modulation) converting unit for performing a conversion of an input signal into a PWM signal; a PWM clock signal generating unit for generating a first clock signal that has a reference period for the conversion into the PWM signal and supplying the first clock signal to the PWM converting unit ;a power switching unit which is supplied power by the switching power supply unit and whose switching is controlled by the PWM signal; and a power supply clock signal generating unit for generating a second clock signal that has a reference period for switching operations of the switching power supply unit and supplying the second clock signal to the switching power supply unit, wherein a starting edge of the second clock signal that is generated by the power supply clock signal generating unit is formed during a period between a movable edge of the PWM signal and a fixed edge that follows the movable edge.
A switching control method according to the present invention is a switching control method for a switching power amplifier that is equipped with a switching power supply unit, and includes a step of controlling a clock signal, which has a reference period for switching operations of the switching power supply unit, so that a starting edge of the clock signal is formed between a movable edge of a PWM signal formed in accordance with an input signal and a fixed edge of the PWM signal that follows the movable edge.
Another switching power amplifier according to the present invention is a switching power amplifier that is equipped with a switching power supply unit and includes: a PWM converting unit for performing a conversion of an input signal into a first PWM signal and a second PWM signal, the first PWM signal and the second PWM signal being a two""s complement of each other; a PWM clock signal generating unit for generating a first clock signal that has a reference period for the conversion into the first PWM signal and the second PWM signal and supplying the first clock signal to the PWM converting unit; a first power switching unit whose switching is controlled by the first PWM signal; a second power switching unit whose switching is controlled by the second PWM signal; a switching power supply unit for supplying power to the first power switching unit and the second power switching unit; and a power supply clock signal generating unit for generating a second clock signal that has a reference period for switching operations of the switching power supply unit and supplying the second clock signal to the switching power supply unit, wherein a starting edge of the second clock signal that is generated by the power supply clock signal generating unit is formed during a period where the first PWM signal and the second PWM signal have an equal potential level.
Another switching control method according to the present invention is a switching control method for a switching power amplifier that is equipped with a switching power supply unit, and includes a step of controlling a clock signal so that a starting edge of the clock signal is formed during one of: a first period between a movable edge of a first PWM signal that is formed in accordance with an input signal and a fixed edge that follows the movable edge; and a second period between a movable edge of a second PWM signal that is a two""s complement of the first PWM signal and a fixed edge that precedes the movable edge.
By being composed as described above, the switching power amplifier and the switching control method for a switching power amplifier according to the present invention each control the cycle of the switching of the switching power supply unit so as to minimize the effects of switching noise of a switching power supply unit, which supplies power, on a power switching circuit of the switching power amplifier. By doing so, the waveform distortion of the PWM power signal that is generated by the power switching circuit can be suppressed, and a sufficient reduction can be made in the signal distortion component of an analog power signal that is outputted to the load based on this PWM power signal.